1. Field of the Invention
This invention relates to a key code generator which has means for sending key code data in a time-divisional manner for storage in key code generator circuits.
2. Description of the Prior Art
In apparatus having a large number of key switches, such as an electronic organ, a very large amount of wiring is required for directly connecting the key switches to desired circuits so that on-off information of the former may be supplied to the latter. To avoid this, there has usually been employed the time division multiplex system in which the on-off information is converted by time-divisional scanning of the key switches into a TDM (Time Division Multiplex) or PCM (Pulse Code Modulation) signal and sent to a key code memory. With this system, however, since the on-off states of the key switches are checked in the time-divisional manner, information of the key switches in the off state is also sent, so that one scanning period is required for sending necessary information, and a clock pulse of a very high frequency, for example, several hundred kilohertzes, is needed for a rapid response to the key depression and release. Further, the response time lags due to the relationship of the moments of key depression and release to one scanning period: for instance, when a depressed key switch is released immediately after being scanned, the response time lags about one scanning period.
To overcome the abovesaid defects, a novel key assignor is proposed in an application filed in Japan under Japanese Pat. application No. 47557/76 entitled "Key Assignor" filed concurrent with the Japanese application corresponding to that of the present application on Apr. 26, 1976 and published in Japan under number 130620/77 on Nov. 2, 1977, and assigned to the same assignee as the present application. The key assignor employs such a key code generator as described in detail in an embodiment of this invention, and is adapted to send the key code of a key switch in the cases of its depression and release without scanning the key switches. In this case, the purpose can well be achieved with clock pulses for simultaneously checking the states of all the key switches and the time for sending their key code data. The abovesaid key assignor has the advantages of a low clock frequency and a very rapid response. In this key assignor, however, input lines of the same number as the key switches must be connected to the latter. In the case of fabricating these circuits as integrated ones, it is necessary to minimize the input lines from the key switches because of a limitation imposed on the number of pins of semiconductor elements.